Semiconductor device

ABSTRACT

According to an embodiment, provided is a semiconductor device includes a semiconductor layer; a first electrode; a second electrode; an electrode pad; a wiring layer electrically connected to the gate electrode; a first polycrystalline silicon layer electrically connected to the electrode pad and the wiring layer; and an insulating layer provided between the first polycrystalline silicon layer and the electrode pad and between the first polycrystalline silicon layer and the wiring layer and having a first opening and a second opening. The electrode pad and the first polycrystalline silicon layer are electrically connected via an inside of the first opening. The wiring layer and the first polycrystalline silicon layer are electrically connected via an inside of the second opening, A first opening area of the first opening is larger than a second opening area of the second opening.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.17/193,765, filed on Mar. 5, 2021, which is based upon and claims thebenefit of priority from Japanese Patent Application No. 2020-157962,filed on Sep. 18, 2020, the entire contents of which are incorporatedherein by reference.

FIELD

Embodiments described herein relate generally to semiconductor devices.

BACKGROUND

In a power module in which a plurality of transistor chips are mountedon a substrate, a gate resistance component may be connected to a gateelectrode pad of each transistor chip. By connecting the gate resistancecomponent, for example, suppression of resonance between the transistorchips and uniform current flow in the power module are implemented.

In a case where the gate resistance component is connected outside thetransistor chip, problems such as an increase in size of the powermodule and a loss of degree of the freedom in arrangement of thetransistor chips in the power module occur. For this reason, in somecases, a gate resistor may be embedded in the transistor chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a portion of asemiconductor device according to a first embodiment;

FIG. 2 is a schematic top view of the semiconductor device according tothe first embodiment;

FIG. 3 is a schematic top view of a portion of the semiconductor deviceaccording to the first embodiment;

FIG. 4 is a schematic cross-sectional view of a portion of thesemiconductor device according to the first embodiment;

FIG. 5 is a schematic top view of a portion of a semiconductor deviceaccording to a second embodiment;

FIG. 6 is a schematic top view of a portion of a semiconductor deviceaccording to a third embodiment;

FIG. 7 is a schematic cross-sectional view of a portion of thesemiconductor device according to the third embodiment;

FIG. 8 is a schematic top view of a portion of a semiconductor deviceaccording to a fourth embodiment;

FIG. 9 is a schematic cross-sectional view of a portion of thesemiconductor device according to the fourth embodiment;

FIG. 10 is a schematic cross-sectional view of a portion of thesemiconductor device according to the fourth embodiment;

FIG. 11 is an explanatory diagram of functions and effects of thesemiconductor device according to the fourth embodiment; and

FIG. 12 is a schematic top view of a portion of a semiconductor deviceaccording to a fifth embodiment.

DETAILED DESCRIPTION

According to an embodiment, there is provided semiconductor deviceincluding: a semiconductor layer having a first face and a second facefacing the first face; a first electrode provided on a side of the firstface of the semiconductor layer; a second electrode provided on a sideof the second face of the semiconductor layer; a gate electrode providedon the side of the first face of the semiconductor layer; an electrodepad being provided on the side of the first face of the semiconductorlayer; a wiring layer provided on the side of the first face of thesemiconductor layer and electrically connected to the gate electrode; afirst polycrystalline silicon layer provided on the side of the firstface of the semiconductor layer, the first polycrystalline silicon layerelectrically connected to the electrode pad and the wiring layer, andthe first polycrystalline silicon layer extending in a first directionparallel to the first face; and an insulating layer provided between thefirst polycrystalline silicon layer and the electrode pad, theinsulating layer provided between the first polycrystalline siliconlayer and the wiring layer, and the insulating layer having at least onefirst opening and at least one second opening, wherein the electrode padand the first polycrystalline silicon layer are electrically connectedvia an inside of the at least one first opening, the wiring layer andthe first polycrystalline silicon layer are electrically connected viaan inside of the at least one second opening, and a first opening areaof the at least one first opening is larger than a second opening areaof the at least one second opening.

Hereinafter, embodiments will be described with reference to thedrawings. In addition, in the following description, the same or similarcomponents and the like will be denoted by the same reference numerals,and the description of the components and the like once described willbe omitted as appropriate.

First Embodiment

A semiconductor device according to a first embodiment includes: asemiconductor layer having a first face and a second face facing thefirst face; a first electrode provided on a side of the first face ofthe semiconductor layer; a second electrode provided on a side of thesecond face of the semiconductor layer; a gate electrode provided on theside of the first face of the semiconductor layer; an electrode padbeing provided on the side of the first face of the semiconductor layer;a wiring layer provided on the side of the first face of thesemiconductor layer and electrically connected to the gate electrode; afirst polycrystalline silicon layer provided on the side of the firstface of the semiconductor layer, the first polycrystalline silicon layerelectrically connected to the electrode pad and the wiring layer, andthe first polycrystalline silicon layer extending in a first directionparallel to the first face; and an insulating layer provided between thefirst polycrystalline silicon layer and the electrode pad, theinsulating layer provided between the first polycrystalline siliconlayer and the wiring layer, and the insulating layer having at least onefirst opening and at least one second opening. The electrode pad and thefirst polycrystalline silicon layer are electrically connected via aninside of the at least one first opening. The wiring layer and the firstpolycrystalline silicon layer are electrically connected via an insideof the at least one second opening. And a first opening area of the atleast one first opening is larger than a second opening area of the atleast one second opening.

The semiconductor device according to the first embodiment is a MOSFET100. The MOSFET 100 is a double implantation MOSFET (DIMOSFET) in whicha base region and a source region are formed by ion implantation. Inaddition, the MOSFET 100 is an n-channel MOSFET having electrons ascarriers.

FIG. 1 is a schematic cross-sectional view of a portion of thesemiconductor device according to the first embodiment. FIG. 2 is aschematic top view of the semiconductor device according to the firstembodiment.

FIG. 1 is a cross-sectional view taken along line AA′ of FIG. 2 . FIG. 2illustrates the overall layout on a first face P1 of FIG. 1 .

As illustrated in FIG. 1 , the MOSFET 100 includes a silicon carbidelayer 10 (semiconductor layer), a source electrode 12 (first electrode),a drain electrode 14 (second electrode), a gate electrode 16, a gateinsulating layer 18, and an interlayer insulating layer 20 (insulatinglayer).

The silicon carbide layer 10 includes an n⁺-type drain region 22, ann⁻-type drift region 24, a p-type body region 26, an n⁺-type sourceregion 28, and a p⁺-type contact region 30.

The silicon carbide layer 10 is disposed between the source electrode 12and the drain electrode 14. The silicon carbide layer 10 includes afirst face (“P1” in FIG. 1 ) and a second face (“P2” in FIG. 1 ).

The second face P2 faces the first face P1. The second face P2 isparallel to the first face P1.

A first direction and a second direction are directions parallel to thefirst face P1. In addition, the second direction is a directionperpendicular to the first direction.

The source electrode 12 is provided on a side of the first face P1 ofthe silicon carbide layer 10. The source electrode 12 is provided on thefirst face P1 of the silicon carbide layer 10. The source electrode 12is in contact with the first face P1.

The source electrode 12 is made of, for example, a metal. The sourceelectrode 12 is electrically connected to the source region 28 and thecontact region 30. The source electrode 12 is in contact with, forexample, the source region 28 and the contact region 30.

The drain electrode 14 is disposed on a side of the second face P2 ofthe silicon carbide layer 10. The drain electrode 14 is provided on thesecond face P2 of the silicon carbide layer 10. The drain electrode 14is in contact with the second face P2.

The drain electrode 14 is made of, for example, a metal or a metalsemiconductor compound. The drain electrode 14 is electrically connectedto the drain region 22. The drain electrode 14 is in contact with, forexample, the drain region 22.

The gate electrode 16 is disposed on the side of the first face P1 ofthe silicon carbide layer 10. The gate electrode 16 extends in, forexample, the second direction.

The gate electrode 16 is a conductive layer. The gate electrode 16 ismade of, for example, polycrystalline silicon containing p-typeimpurities or n-type impurities.

The gate insulating layer 18 is disposed between the gate electrode 16and the silicon carbide layer 10. The gate insulating layer 18 is, forexample, a silicon oxide film.

The interlayer insulating layer 20 is provided on the gate electrode 16.The interlayer insulating layer 20 is provided between the gateelectrode 16 and the source electrode 12. The interlayer insulatinglayer 20 electrically separates the gate electrode 16 and the sourceelectrode 12. The interlayer insulating layer 20 is, for example, asilicon oxide film.

As illustrated in FIG. 2 , the MOSFET 100 includes the source electrode12 (first electrode), a gate electrode pad 32 (electrode pad), and agate wiring layer 34 (wiring layer).

The gate electrode pad 32 is provided on the side of the first face P1of the silicon carbide layer 10. A bonding wire can be connected on thegate electrode pad 32. The gate electrode pad 32 is connected to, forexample, a gate driver circuit by using the bonding wire. A gate voltageis applied to the gate electrode pad 32 from the gate driver circuit viathe bonding wire.

The gate electrode pad 32 is made of, for example, the same material asthe source electrode 12. The gate electrode pad 32 is formed in, forexample, the same layer as the source electrode 12. The gate electrodepad 32 is made of, for example, a metal.

The gate wiring layer 34 is provided on the side of the first face P1 ofthe silicon carbide layer 10. The gate wiring layer 34 is made of, forexample, the same material as the source electrode 12 and the gateelectrode pad 32. The gate electrode pad 32 is formed in, for example,the same layer as the source electrode 12 and the gate electrode pad 32.The gate electrode pad 32 is made of, for example, a metal.

A portion of the gate wiring layer 34 is provided adjacent to, forexample, the gate electrode pad 32. A portion of the gate wiring layer34 is provided along, for example, the gate electrode pad 32.

The gate wiring layer 34 is electrically connected to the gate electrode16.

FIG. 3 is a schematic top view of a portion of the semiconductor deviceaccording to the first embodiment. FIG. 3 illustrates a pattern layoutof a region X surrounded by a broken line in FIG. 2 .

FIG. 4 is a schematic cross-sectional view of a portion of thesemiconductor device according to the first embodiment. FIG. 4 is across-sectional view taken along line BB′ of FIG. 3 .

As illustrated in FIGS. 1 to 4 , the MOSFET 100 includes a siliconcarbide layer 10 (semiconductor layer), a source electrode 12 (firstelectrode), an interlayer insulating layer 20 (insulating layer), a gateelectrode pad 32 (electrode pad), a gate wiring layer 34 (wiring layer),a plurality of first polycrystalline silicon layers 41, and a fieldinsulating layer 44. The interlayer insulating layer 20 has a firstcontact hole 20 a (first opening) and a second contact hole 20 b (secondopening).

The field insulating layer 44 is provided on the silicon carbide layer10. The field insulating layer 44 is, for example, a silicon oxide film.

The first polycrystalline silicon layer 41 is provided on the siliconcarbide layer 10. The first polycrystalline silicon layer 41 is providedon the field insulating layer 44.

The first polycrystalline silicon layer 41 is electrically connected tothe gate electrode pad 32 and the gate wiring layer 34. The gateelectrode pad 32, the first polycrystalline silicon layer 41, the gatewiring layer 34, and the gate electrode 16 are connected in series. Thefirst polycrystalline silicon layer 41 functions as a gate resistorembedded in the MOSFET 100.

The first polycrystalline silicon layer 41 extends in the firstdirection. A length (L in FIG. 3 ) of the first polycrystalline siliconlayer 41 in the first direction is, for example, 200 μm or more and 500μm or less. A width (W in FIG. 3 ) of the first polycrystalline siliconlayer 41 in the second direction is, for example, 20 μm or more and 50μm or less.

The first polycrystalline silicon layer 41 contains p-type impurities orn-type impurities. The p-type impurity is, for example, boron (B). Then-type impurity is, for example, phosphorus (P) or arsenic (As).

The first polycrystalline silicon layer 41 is made of, for example, thesame material as the gate electrode 16. The first polycrystallinesilicon layer 41 is formed in, for example, the same layer as the gateelectrode 16.

The interlayer insulating layer 20 is provided between the firstpolycrystalline silicon layer 41 and the gate electrode pad 32. Theinterlayer insulating layer 20 is provided between the firstpolycrystalline silicon layer 41 and the gate wiring layer 34.

The interlayer insulating layer 20 has a first contact hole 20 a and asecond contact hole 20 b. The first contact hole 20 a and the secondcontact hole 20 b have hole patterns provided in the interlayerinsulating layer 20.

A first opening area of the first contact hole 20 a is larger than asecond opening area of the second contact hole 20 b. The first openingarea is, for example, twice or more and ten times or less of the secondopening area.

The first opening area of the first contact hole 20 a denotes an area ofa region surrounded by a wall surface of the first contact hole 20 aamong the surfaces parallel to the first face P1. The first opening areaof the first contact hole 20 a is, for example, the area of a squareillustrated the first contact hole 20 a in FIG. 3 .

Similarly, the second opening area of the second contact hole 20 bdenotes an area of a region surrounded by a wall surface of the secondcontact hole 20 b among the surfaces parallel to the first face P1. Thesecond opening area of the second contact hole 20 b is, for example, thearea of a square illustrated the second contact hole 20 b in FIG. 3 .

The gate electrode pad 32 and the first polycrystalline silicon layer 41are electrically connected via the first contact hole 20 a. For example,since the gate electrode pad 32 entering the first contact hole 20 a isin contact with the first polycrystalline silicon layer 41 at the bottomof the first contact hole 20 a, the gate electrode pad 32 and the firstpolycrystalline silicon layer 41 are electrically connected.

The gate wiring layer 34 and the first polycrystalline silicon layer 41are electrically connected via the second contact hole 20 b. Forexample, since the gate wiring layer 34 entering the second contact hole20 b is in contact with the first polycrystalline silicon layer 41 atthe bottom of the second contact hole 20 b, the gate wiring layer 34 andthe first polycrystalline silicon layer 41 are electrically connected.

A distance (d in FIG. 3 ) between the first contact hole 20 a and thesecond contact hole 20 b is, for example, 100 μm or more and 300 μm orless.

Next, functions and effects of the semiconductor device according to thefirst embodiment will be described.

In a power module in which a plurality of transistor chips are mountedon a substrate, a gate resistance component may be connected to the gateelectrode pad of each transistor chip. By connecting the gate resistancecomponent, for example, suppression of resonance between the transistorchips and uniform current in the power module are implemented.

In a case where the gate resistance component is connected outside thetransistor chip, problems such as an increase in size of the powermodule and a loss of the degree of freedom in arrangement of thetransistor chips in the power module occur. For this reason, in somecases, the gate resistor may be embedded in the transistor chip.

However, the temperature rises due to the heat generated by the embeddedgate resistor, and thus, there is a concern that a fluctuation incharacteristics of the transistor occurs or the transistor isdestructed.

For example, the resistance value of the gate resistor changes by thetemperature rise due to the heat generation of the gate resistor, andthus, the fluctuation in characteristics of the transistor occurs. Inaddition, for example, by the temperature rise due to the heatgeneration of the gate resistor, the gate resistor is melted and cut,and thus, the transistor is destructed.

In the MOSFET 100 according to the first embodiment, the first openingarea of the first contact hole 20 a for connecting the gate electrodepad 32 and the first polycrystalline silicon layer 41 is larger than thesecond opening area of the second contact hole 20 b for connecting thegate wiring layer 34 and the first polycrystalline silicon layer 41.

Since the first opening area of the first contact hole 20 a is large,the heat generated in the first polycrystalline silicon layer 41 easilyflows to the gate electrode pad 32.

The gate electrode pad 32 has a larger area than the gate wiring layer34. For this reason, the gate electrode pad 32 has a higher heatdissipation efficiency than the gate wiring layer 34. In addition, in astate where the MOSFET 100 is mounted on the power module, for example,a bonding wire is connected to the gate electrode pad 32. For thisreason, the gate electrode pad 32 can be expected to dissipate heatthrough the bonding wire. In addition, since it is necessary to performbonding on the gate electrode pad 32, a protective film is not formed.Therefore, the heat dissipation efficiency is higher than that of thegate wiring layer 34 on which the protective film is formed.

The heat generated in the first polycrystalline silicon layer 41 moreeasily flows to the gate electrode pad 32 than the gate wiring layer 34,so that the temperature rise of the first polycrystalline silicon layer41 is suppressed. Therefore, the fluctuation in characteristics anddestruction of the MOSFET 100 are suppressed.

From the viewpoint of suppressing the temperature rise of the firstpolycrystalline silicon layer 41, the first opening area is preferablytwice or more, more preferably four times or more of the second openingarea.

As described above, according to the first embodiment, it is possible toprovide a semiconductor device in which the temperature rise of theembedded gate resistor is suppressed.

Second Embodiment

A semiconductor device according to a second embodiment is differentfrom the semiconductor device according to the first embodiment in thatthe number of at least one first opening is larger than the number of atleast one second opening. Hereinafter, some descriptions of the contentsoverlapping with the first embodiment will be omitted.

The semiconductor device according to the second embodiment is a MOSFET200.

FIG. 5 is a schematic top view of a portion of the semiconductor deviceaccording to the second embodiment. FIG. 5 is a diagram corresponding toFIG. 3 of the first embodiment.

As illustrated in FIG. 5 , in the MOSFET 200 according to the secondembodiment, the number of first contact holes 20 a is larger than thenumber of second contact holes 20 b. The number of first contact holes20 a corresponding to one first polycrystalline silicon layer 41 isfour, and the number of second contact holes 20 b is one.

When a plurality of the first contact holes 20 a are provided, a firstopening area of the first contact holes 20 a is the sum of the openingareas of the individual first contact holes 20 a. Similarly, when aplurality of the second contact holes 20 b are provided, a secondopening area of the second contact holes 20 b is the sum of the openingareas of the individual second contact holes 20 b.

In the case of FIG. 5 , the first opening area of the first contact hole20 a is four times of the second opening area of the second contact hole20 b.

As described above, according to the second embodiment, similarly to thefirst embodiment, it is possible to provide the semiconductor device inwhich a temperature rise of an embedded gate resistor is suppressed.

Third Embodiment

A semiconductor device according to a third embodiment is different fromthe semiconductor device according to the first embodiment in that thesemiconductor device according to the third embodiment further includesa second polycrystalline silicon layer provided on a side of a firstface of a semiconductor layer, the second polycrystalline silicon layerelectrically connected to an electrode pad, the second polycrystallinesilicon layer electrically separated from a wiring layer, and the secondpolycrystalline silicon layer extending in a first direction.Hereinafter, some descriptions of the contents overlapping with thefirst embodiment will be omitted.

The semiconductor device according to the third embodiment is a MOSFET300.

FIG. 6 is a schematic top view of a portion of the semiconductor deviceaccording to the third embodiment.

FIG. 6 is a diagram corresponding to FIG. 3 of the first embodiment.

FIG. 7 is a schematic cross-sectional view of a portion of thesemiconductor device according to the third embodiment. FIG. 7 is across-sectional view taken along line CC′ of FIG. 6 .

As illustrated in FIGS. 6 and 7 , the MOSFET 300 according to the thirdembodiment includes a second polycrystalline silicon layer 42 inaddition to a first polycrystalline silicon layer 41. The secondpolycrystalline silicon layer 42 is provided on the side of a first faceP1 of a silicon carbide layer 10. The second polycrystalline siliconlayer 42 extends in the first direction.

The second polycrystalline silicon layer 42 is electrically connected toa gate electrode pad 32. The second polycrystalline silicon layer 42 iselectrically separated from a gate wiring layer 34.

A contact hole for electrically connecting the gate wiring layer 34 andthe second polycrystalline silicon layer 42 is not provided to aninterlayer insulating layer 20.

Since the MOSFET 300 according to the third embodiment includes thesecond polycrystalline silicon layer 42 which is electrically separatedfrom a gate wiring layer 34, it is possible to set a gate resistor tohave a higher resistance value than that of the MOSFET 100 according tothe first embodiment.

As described above, according to the third embodiment, similarly to thefirst embodiment, it is possible to provide the semiconductor device inwhich a temperature rise of the embedded gate resistor is suppressed.

Fourth Embodiment

A semiconductor device according to a fourth embodiment includes: asemiconductor layer having a first face and a second face facing thefirst face; a first electrode being provided on a side of the first faceof the semiconductor layer; a second electrode being provided on a sideof the second face of the semiconductor layer; a gate electrode beingprovided on the side of the first face of the semiconductor layer; anelectrode pad being provided on the side of the first face of thesemiconductor layer; a wiring layer being provided on the side of thefirst face of the semiconductor layer and being electrically connectedto the gate electrode; a first polycrystalline silicon layer beingprovided on the side of the first face of the semiconductor layer, beingelectrically connected to the electrode pad and the wiring layer,extending in a first direction parallel to the first face, and includinga first p-type region and a first n-type region; a secondpolycrystalline silicon layer being provided on the side of the firstface of the semiconductor layer, being electrically connected to theelectrode pad and the wiring layer, extending in the first direction,including a second n-type region and a second p-type region, and beingseparated from the first polycrystalline silicon layer; and aninsulating layer being provided between the first polycrystallinesilicon layer and the electrode pad, between the second polycrystallinesilicon layer and the electrode pad, between the first polycrystallinesilicon layer and the wiring layer, between the second polycrystallinesilicon layer and the wiring layer, and including at least one firstopening, at least one second opening, at least one third opening, and atleast one fourth opening, wherein the electrode pad and the first p-typeregion are electrically connected via the at least one first opening,wherein the wiring layer and the first n-type region are electricallyconnected via the at least one second opening, wherein the electrode padand the second n-type region are electrically connected via the at leastone third opening, wherein the wiring layer and the second p-type regionare electrically connected via the at least one fourth opening, whereina first distance between a first junction plane of the first p-typeregion and the first n-type region and the at least one first opening issmaller than a second distance between the first junction plane and theat least one second opening, and wherein a third distance between asecond junction plane of the second n-type region and the second p-typeregion and the at least one third opening is smaller than a fourthdistance between the second junction plane and the at least one fourthopening. Hereinafter, in some cases, some descriptions of the contentsoverlapping with the first embodiment will be omitted.

The semiconductor device according to the fourth embodiment is a MOSFET400. The MOSFET 400 has a transistor structure similar to the structureillustrated in FIG. 1 of the first embodiment.

FIG. 8 is a schematic top view of a portion of the semiconductor deviceaccording to the fourth embodiment. FIG. 8 is a diagram corresponding toFIG. 3 of the first embodiment.

FIG. 9 is a schematic cross-sectional view of a portion of thesemiconductor device according to the fourth embodiment. FIG. 9 is across-sectional view taken along line DD′ of FIG. 8 .

FIG. 10 is a schematic cross-sectional view of a portion of thesemiconductor device according to the fourth embodiment. FIG. 10 is across-sectional view taken along line EE′ of FIG. 8 .

As illustrated in FIGS. 8, 9 and 10 , the MOSFET 400 includes a siliconcarbide layer 10 (semiconductor layer), a source electrode 12 (firstelectrode), an interlayer insulating layer 20 (insulating layer), a gateelectrode pad 32 (electrode pad), a gate wiring layer 34 (wiring layer),a plurality of first polycrystalline silicon layers 51, a plurality ofsecond polycrystalline silicon layers 52, and a field insulating layer44. The interlayer insulating layer 20 includes a first contact hole 20a (first opening), a second contact hole 20 b (second opening), a thirdcontact hole 20 c (third opening), and a fourth contact hole 20 d(fourth opening).

The field insulating layer 44 is provided on the silicon carbide layer10. The field insulating layer 44 is, for example, a silicon oxide film.

The first polycrystalline silicon layer 51 and the secondpolycrystalline silicon layer 52 are provided on the silicon carbidelayer 10. The first polycrystalline silicon layer 51 and the secondpolycrystalline silicon layer 52 are provided on the field insulatinglayer 44.

The first polycrystalline silicon layer 51 and the secondpolycrystalline silicon layer 52 are electrically connected to the gateelectrode pad 32 and the gate wiring layer 34. The gate electrode pad32, the first polycrystalline silicon layer 51, the gate wiring layer34, and the gate electrode 16 are connected in series. The gateelectrode pad 32, the second polycrystalline silicon layer 52, the gatewiring layer 34, and the gate electrode 16 are connected in series. Thefirst polycrystalline silicon layer 51 and the second polycrystallinesilicon layer 52 function as gate resistors embedded in the MOSFET 400.

The first polycrystalline silicon layer 51 extends in the firstdirection. A length of the first polycrystalline silicon layer 51 in thefirst direction is, for example, 200 μm or more and 500 μm or less. Awidth of the first polycrystalline silicon layer 51 in the seconddirection is, for example, 20 μm or more and 50 μm or less.

The first polycrystalline silicon layer 51 includes a first p-typeregion 51 a and a first n-type region 51 b. The first polycrystallinesilicon layer 51 functions as a gate resistor with a pn diode.

The first p-type region 51 a contains p-type impurities. The p-typeimpurity is, for example, boron (B).

The first n-type region 51 b contains n-type impurities. The n-typeimpurity is, for example, phosphorus (P) or arsenic (As).

The second polycrystalline silicon layer 52 extends in the firstdirection. The second polycrystalline silicon layer 52 is separated fromthe first polycrystalline silicon layer 51. A length of the secondpolycrystalline silicon layer 52 in the first direction is, for example,200 μm or more and 500 μm or less. A width of the second polycrystallinesilicon layer 52 in the second direction is, for example, 20 μm or moreand 50 μm or less.

The second polycrystalline silicon layer 52 includes a second n-typeregion 52 a and a second p-type region 52 b. The second polycrystallinesilicon layer 52 functions as a gate resistor with a pn diode.

The second n-type region 52 a contains n-type impurities. The n-typeimpurity is, for example, phosphorus (P) or arsenic (As).

The second p-type region 52 b contains p-type impurities. The p-typeimpurity is, for example, boron (B).

The interlayer insulating layer 20 is provided between the firstpolycrystalline silicon layer 51 and the gate electrode pad 32 andbetween the second polycrystalline silicon layer 52 and the gateelectrode pad 32. The interlayer insulating layer 20 is provided betweenthe first polycrystalline silicon layer 51 and the gate wiring layer 34and between the second polycrystalline silicon layer 52 and the gatewiring layer 34.

The interlayer insulating layer 20 has a first contact hole 20 a, asecond contact hole 20 b, a third contact hole 20 c, and a fourthcontact hole 20 d. The first contact hole 20 a, the second contact hole20 b, the third contact hole 20 c, and the fourth contact hole 20 d arehole patterns provided in the interlayer insulating layer 20.

The gate electrode pad 32 and the first p-type region 51 a areelectrically connected via the first contact hole 20 a. For example,since the gate electrode pad 32 entering the first contact hole 20 a isin contact with the first p-type region 51 a at the bottom of the firstcontact hole 20 a, the gate electrode pad 32 and the first p-type region51 a are electrically connected.

The gate wiring layer 34 and the first n-type region 51 b areelectrically connected via the second contact hole 20 b. For example,since the gate wiring layer 34 entering the second contact hole 20 b isin contact with the first n-type region 51 b at the bottom of the secondcontact hole 20 b, the gate wiring layer 34 and the first n-type region51 b are electrically connected.

A distance between the first contact hole 20 a and the second contacthole 20 b is, for example, 100 μm or more and 300 μm or less.

A boundary between the first p-type region 51 a and the first n-typeregion 51 b is a first junction plane 51 x. The first junction plane 51x is a pn junction.

A first distance (d1 in FIG. 8 ) between the first junction plane 51 xand the first contact hole 20 a is smaller than a second distance (d2 inFIG. 8 ) between the first junction plane 51 x and the second contacthole 20 b. The first distance d1 is, for example, one-half or less ofthe second distance d2.

The gate electrode pad 32 and the second n-type region 52 a areelectrically connected via the third contact hole 20 c. For example,since the gate electrode pad 32 entering the third contact hole 20 c isin contact with the second n-type region 52 a at the bottom of the thirdcontact hole 20 c, the gate electrode pad 32 and the second n-typeregion 52 a are electrically connected.

The gate wiring layer 34 and the second p-type region 52 b areelectrically connected via the fourth contact hole 20 d. For example,since the gate wiring layer 34 entering the fourth contact hole 20 d isin contact with the second p-type region 52 b at the bottom of thefourth contact hole 20 d, the gate wiring layer 34 and the second p-typeregion 52 b are electrically connected.

A distance between the third contact hole 20 c and the fourth contacthole 20 d is, for example, 100 μm or more and 300 μm or less.

A boundary between the second n-type region 52 a and the second p-typeregion 52 b is a second junction plane 52 x. The second junction plane52 x is a pn junction.

A third distance (d3 in FIG. 8 ) between the second junction plane 52 xand the third contact hole 20 c is smaller than a fourth distance (d4 inFIG. 8 ) between the second junction plane 52 x and the fourth contacthole 20 d. The third distance d3 is, for example, one-half or less ofthe fourth distance d4.

Next, functions and effects of the semiconductor device according to thefirst embodiment will be described.

FIG. 11 is an explanatory diagram of functions and effects of thesemiconductor device according to the fourth embodiment. FIG. 11illustrates an equivalent circuit diagram including the gate resistorsof the MOSFET 400.

In the MOSFET 400, different resistance values of the gate resistor canbe applied at the time of the turn-on operation of the transistor and atthe time of the turn-off operation of the transistor. In other words, anoptimum resistance value of the gate resistor can be applied at the timeof the turn-on operation of the transistor and at the time of theturn-off operation of the transistor.

For example, at the time of the turn-on operation in which the gatevoltage Vg applied to the gate electrode pad 32 becomes a positivevoltage with respect to the gate electrode 16, only the firstpolycrystalline silicon layer 51 functions as a gate resistor.

On the other hand, for example, at the time of the turn-off operation inwhich the gate voltage Vg applied to the gate electrode pad 32 becomes anegative voltage with respect to the gate electrode 16, only the secondpolycrystalline silicon layer 52 functions as a gate resistor.

As illustrated in FIG. 8 , in the fourth embodiment, the number of firstpolycrystalline silicon layers 51 connected in parallel is two, and thenumber of second polycrystalline silicon layers 52 connected in parallelis four. For this reason, in a case where the resistance value of eachof the first polycrystalline silicon layer 51 and the secondpolycrystalline silicon layer 52 is the same, the resistance value atthe time of the turn-on operation of the transistor is larger than theresistance value at the time of the turn-off operation. For example, byincreasing the resistance value at the time of the turn-on operation ofthe transistor, the resonance between the transistor chips can besuppressed. For example, a turn-off loss can be reduced by decreasingthe resistance value at the time of the turn-off operation of thetransistor.

In the MOSFET 400, the temperature of the first polycrystalline siliconlayer 51 or the second polycrystalline silicon layer 52 rises due to theheat generated by the diode, and thus, there is a concern that afluctuation in characteristics of the transistor occurs or thetransistor is destructed.

In the MOSFET 400 according to the fourth embodiment, the first distance(d1 in FIG. 8 ) between the first junction plane 51 x and the firstcontact hole 20 a is smaller than the second distance (d2 in FIG. 8 )between the first junction plane 51 x and the second contact hole 20 b.For this reason, the first contact hole 20 a connected to the gateelectrode pad 32 is provided at a location close to the pn junction ofthe diode.

Since the pn junction of the diode is close to the first contact hole 20a, the heat generated by the diode of the first polycrystalline siliconlayer 51 easily flows to the gate electrode pad 32.

In addition, in the MOSFET 400 according to the fourth embodiment, thethird distance (d3 in FIG. 8 ) between the second junction plane 52 xand the third contact hole 20 c is smaller than the fourth distance (d4in FIG. 8 ) between the second junction plane 52 x and the fourthcontact hole 20 d. For this reason, the third contact hole 20 cconnected to the gate electrode pad 32 is provided at a location closeto the pn junction of the diode.

Since the pn junction of the diode is close to the third contact hole 20c, the heat generated by the diode of the second polycrystalline siliconlayer 52 easily flows to the gate electrode pad 32.

The gate electrode pad 32 has a larger area than the gate wiring layer34. For this reason, the gate electrode pad 32 has a higher heatdissipation efficiency than the gate wiring layer 34. In addition, in astate where the MOSFET 400 is mounted on the power module, for example,a bonding wire is connected to the gate electrode pad 32. The gateelectrode pad 32 can be expected to dissipate heat through the bondingwire. In addition, a protective film is not formed on the gate electrodepad 32 for performing bonding. Therefore, the heat dissipationefficiency is higher than that of the gate wiring layer 34 on which theprotective film is formed.

The heat generated by the diodes of the first polycrystalline siliconlayer 51 and the second polycrystalline silicon layer 52 easily flows tothe gate electrode pad 32, so that a temperature rise of the firstpolycrystalline silicon layer 51 and the second polycrystalline siliconlayer 52 is suppressed. Therefore, the fluctuation in characteristicsand the of the MOSFET 400 are suppressed.

From the viewpoint of suppressing the temperature rise of the firstpolycrystalline silicon layer 51, the first distance d1 is preferablyone-half or less of the second distance d2, more preferably one-fourthor less of the second distance d2. In addition, from the viewpoint ofsuppressing the temperature rise of the second polycrystalline siliconlayer 52, the third distance d3 is preferably one-half or less of thefourth distance d4, more preferably one-fourth or less of the fourthdistance d4.

In addition, in FIG. 8 , the case of changing the resistance value atthe time of the turn-on operation of the transistor and the resistancevalue at the time of the turn-off operation of the transistor bychanging the number of the first polycrystalline silicon layers 51 andthe number of the second polycrystalline silicon layers 52 connected inparallel has been described as an example. However, for example, theresistance value at the time of the turn-on operation of the transistorand the resistance value at the time of the turn-off operation of thetransistor may be allowed to be changed by changing the resistance valueof each of the first polycrystalline silicon layer 51 and the secondpolycrystalline silicon layer 52.

In addition, the case where the resistance value at the time of theturn-on operation of the transistor is allowed to be larger than theresistance value at the time of the turn-off operation is described asan example, but the resistance value at the time of the turn-onoperation of the transistor may be allowed to be smaller than theresistance value at the time of the turn-off operation.

As described above, according to the fourth embodiment, it is possibleto provide a semiconductor device in which the temperature rise of theembedded gate resistor is suppressed.

Fifth Embodiment

A semiconductor device according to a fifth embodiment is different fromthe semiconductor device according to the fourth embodiment in that afirst opening area of at least one first opening is larger than a secondopening area of at least one second opening, and a third opening area ofat least one third opening is larger than a fourth opening area of atleast one fourth opening. Hereinafter, in some cases, some descriptionsof the contents overlapping with the fourth embodiment will be omitted.

The semiconductor device according to the fifth embodiment is a MOSFET500.

FIG. 12 is a schematic top view of a portion of the semiconductor deviceaccording to the fifth embodiment. FIG. 12 is a diagram corresponding toFIG. 8 of the fourth embodiment.

As illustrated in FIG. 12 , in the MOSFET 500 according to the fifthembodiment, a first opening area of a first contact hole 20 a is largerthan a second opening area of a second contact hole 20 b. Since thefirst opening area of the first contact hole 20 a is large, the heatgenerated in a first polycrystalline silicon layer 51 easily flows to agate electrode pad 32.

In addition, a third opening area of a third contact hole 20 c is largerthan a fourth opening area of a fourth contact hole 20 d. Since thethird opening area of the third contact hole 20 c is large, the heatgenerated in a second polycrystalline silicon layer 52 easily flows to agate electrode pad 32.

Therefore, the MOSFET 500 according to the fifth embodiment can furthersuppress a temperature rise of the first polycrystalline silicon layer51 and the second polycrystalline silicon layer 52 as compared with theMOSFET 400 according to the fourth embodiment.

As described above, according to the fifth embodiment, it is possible toprovide the semiconductor device in which a temperature rise of anembedded gate resistor is suppressed.

As described above, in the first to fifth embodiments, the n-channelMOSFETs are described as examples, but the embodiments can also beapplied to p-channel MOSFETs.

In addition, in the first to fifth embodiments, the MOSFETs having aplanar gate structure in which a gate electrode is provided on a firstface of a semiconductor layer are described as examples, but theembodiments can also be applied to MOSFETs having a trench gatestructure in which the gate electrode is provided in a trench formed inthe semiconductor layer.

In addition, the embodiments can also be applied to an insulated gatebipolar transistor (IGBT).

In addition, in the first to fifth embodiments, the case where siliconcarbide is used for the semiconductor layer is described as an example,but the semiconductor layer may be another semiconductor such assilicon.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the semiconductor devices describedherein may be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the devices andmethods described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor layer having a first face and a second face facing thefirst face; a first electrode provided on a side of the first face ofthe semiconductor layer; a second electrode provided on a side of thesecond face of the semiconductor layer; a gate electrode provided on theside of the first face of the semiconductor layer; an electrode padbeing provided on the side of the first face of the semiconductor layer;a wiring layer provided on the side of the first face of thesemiconductor layer and electrically connected to the gate electrode; afirst polycrystalline silicon layer provided on the side of the firstface of the semiconductor layer, the first polycrystalline silicon layerelectrically connected to the electrode pad and the wiring layer, andthe first polycrystalline silicon layer extending in a first directionparallel to the first face; and an insulating layer provided between thefirst polycrystalline silicon layer and the electrode pad, theinsulating layer provided between the first polycrystalline siliconlayer and the wiring layer, and the insulating layer having at least onefirst opening and at least one second opening, wherein the electrode padand the first polycrystalline silicon layer are electrically connectedvia an inside of the at least one first opening, the wiring layer andthe first polycrystalline silicon layer are electrically connected viaan inside of the at least one second opening, and a first opening areaof the at least one first opening is larger than a second opening areaof the at least one second opening.
 2. The semiconductor deviceaccording to claim 1, wherein a length of the first polycrystallinesilicon layer in the first direction is 200 μm or more, and a width ofthe first polycrystalline silicon layer in a second direction parallelto the first face and perpendicular to the first direction is 50 μm orless.
 3. The semiconductor device according to claim 1, wherein thefirst opening area is twice or more the second opening area.
 4. Thesemiconductor device according to claim 1, wherein a number of the atleast one first opening is larger than a number of the at least onesecond opening.
 5. The semiconductor device according to claim 1,wherein the electrode pad is in contact with the first polycrystallinesilicon layer, and the wiring layer is in contact with the firstpolycrystalline silicon layer.
 6. The semiconductor device according toclaim 1, further comprising a second polycrystalline silicon layerprovided on the side of the first face of the semiconductor layer, thesecond polycrystalline silicon layer electrically connected to theelectrode pad, the second polycrystalline silicon layer electricallyseparated from the wiring layer, and the second polycrystalline siliconlayer extending in the first direction.
 7. The semiconductor deviceaccording to claim 1, wherein the first polycrystalline silicon layercontains p-type impurities or n-type impurities.
 8. The semiconductordevice according to claim 1, wherein the semiconductor layer is asilicon carbide layer.
 9. A semiconductor device comprising: asemiconductor layer having a first face and a second face facing thefirst face; a first electrode provided on a side of the first face ofthe semiconductor layer; a second electrode provided on a side of thesecond face of the semiconductor layer; a gate electrode provided on theside of the first face of the semiconductor layer; an electrode padprovided on the side of the first face of the semiconductor layer; awiring layer provided on the side of the first face of the semiconductorlayer and electrically connected to the gate electrode; a firstpolycrystalline silicon layer provided on the side of the first face ofthe semiconductor layer, the first polycrystalline silicon layerelectrically connected to the electrode pad and the wiring layer, thefirst polycrystalline silicon layer extending in a first directionparallel to the first face, and the first polycrystalline silicon layerincluding a first p-type region and a first n-type region; a secondpolycrystalline silicon layer provided on the side of the first face ofthe semiconductor layer, the second polycrystalline silicon layerelectrically connected to the electrode pad and the wiring layer, thesecond polycrystalline silicon layer extending in the first direction,the second polycrystalline silicon layer including a second n-typeregion and a second p-type region, and the second polycrystallinesilicon layer separated from the first polycrystalline silicon layer;and an insulating layer provided between the first polycrystallinesilicon layer and the electrode pad, the insulating layer providedbetween the second polycrystalline silicon layer and the electrode pad,the insulating layer provided between the first polycrystalline siliconlayer and the wiring layer, the insulating layer provided between thesecond polycrystalline silicon layer and the wiring layer, and theinsulating layer including at least one first opening, the insulatinglayer including at least one second opening, the insulating layerincluding at least one third opening, and the insulating layer includingat least one fourth opening, wherein the electrode pad and the firstp-type region are electrically connected via the at least one firstopening, the wiring layer and the first n-type region are electricallyconnected via the at least one second opening, the electrode pad and thesecond n-type region are electrically connected via the at least onethird opening, the wiring layer and the second p-type region areelectrically connected via the at least one fourth opening, a firstdistance between a first junction plane of the first p-type region andthe first n-type region and the at least one first opening is smallerthan a second distance between the first junction plane and the at leastone second opening, and a third distance between a second junction planeof the second n-type region and the second p-type region and the atleast one third opening is smaller than a fourth distance between thesecond junction plane and the at least one fourth opening.
 10. Thesemiconductor device according to claim 9, wherein a first opening areaof the at least one first opening is larger than a second opening areaof the at least one second opening, and a third opening area of the atleast one third opening is larger than a fourth opening area of the atleast one fourth opening.
 11. The semiconductor device according toclaim 9, wherein the first distance is one-half or less of the seconddistance, and the third distance is one-half or less of the fourthdistance.
 12. The semiconductor device according to claim 9, wherein thesemiconductor layer is a silicon carbide layer.